This invention relates to digital phase shift circuits. More particularly, this invention relates to a digital phase shifter, incorporating the concepts of interpolation and decimation, which can supply a delay or linear phase shift that is a non-integer multiple of the sampling period of the applied signal.
Linear phase shift or delay of a signal waveform is often necessary in digital signal processing systems. In applications where the desired delay is an integer multiple of the system sampling period, prior art digital phase shifters have generally comprised cascade arrangements of unit delay networks. In applications such as the interfacing of a digital processing system with an analog system, it is often necessary to provide delays which are non-integer multiples of the digital sampling rate. For example, in the cancellation of echoes, digital systems are often used to generate artificial echoes by means of simulation of an echo. These artificial echoes are then subtracted from the original analog signal to effect echo cancellation. To provide the most satisfactory result, the simulated digital echo may have to be delayed by a non-integer multiple of the sampling period. A second instance in which a non-integer delay is required occurs when a plurality of signals must be processed simultaneously, such as in a phased array antenna system.
Recently, the concepts of decimation and interpolation as taught by R. W. Schafer and L. R. Rabiner in "A Digital Signal Processing Approach to Interpolation," Proceedings of the IEEE, Vol. 6, No. 6, pages ) -707, June, 1973, have provided digital signal processing techniques applicable to realizing a digital phase shifter which is capable of non-integer delay. Interpolation and decimation are terms which respectively describe x(n), rate increase and decrease -1),...,integer factors. In a digital phase shifter utilizing interpolation and decimation, the sampling rate is increased by a factor D by adding D-1 zero-valued samples between adjacent samples of the original signal. The resulting signal is then filtered by a low-pass filter to remove the periodic frequency components which are centered about integer multiples of the original sampling frequency. The interpolated signal is then delayed an integer number of samples, p, at the higher sampling rate and the signal is then restored to the original sampling rate by a decimation circuit which effectively selects every Dth sample of the delayed interpolated signal to provide a non-integer delay of p/D T where T is the sampling period of the original signal, D is the decimation and interpolation factor, and p is the integer delay at the higher sampling rate. Although such a system is generally satisfactory, the use of two different sampling rates results in a fairly complex structure.
Accordingly, it is an object of this invention to realize a digital phase shifter which operates at the same sampling rate as the system in which it is employed and is capable of providing non-integer delay.